1. Technical Field
The present invention relates generally to a three-dimensional package for massive layers of integrated circuit (IC) chips, on which logic circuits and/or memory arrays are disposed and interconnected in a novel way to permit addressing (i.e. selection) of the circuits and/or arrays on these circuit layers using a minimum number of connections and with the shortest propagation delays.
2. Brief Description of Prior Art
Today, most electronic packages are largely two-dimensional in arrangement. Typically, multiple chips are placed on a single planar module called a Multiple Chip Module (MCM). These modules are coarse in granularity, with feature sizes of 5 to 10 mils. Because of this coarse granularity, many metallization levels are required to wire the module. Typically, this category of IC packaging involves twenty to forty levels of metallization.
To reduce the number of metal layers, and thereby improve performance, newer 2-D modules use finer features such as thin-film wiring with line widths on the order of 10 to 20 xcexcm. A typical arrangement is to place four chips on a single module to comprise a single microprocessor (MP). One chip is the computer (CPU), one chip is the storage control unit (SCU), while the remaining two chips are the cache memory. The average chip has dimensions of about 10 mmxc3x9710 mm. To allow for reasonable wiring, the module is likely to be 40 mmxc3x9740 mm. Even if placement algorithms are used to arrange chips and the function on the chips, typical chip-to-chip signal paths are of the order of the chip size, say 10 mm, For a transmission line of 15 xcexcm width and lengths greater than 10 mm, line resistance becomes important and wiring rules are needed to restrict the signal length to achieve reasonable delays. Notably, the signal path length to main memory is much larger.
The MCMs described above are typically mounted on a card, and then the card is mounted on a board. Thus, the module is considered the first package level, the card the second level, and the board the third level. Clearly, there is much wasted space using such an arrangement that an opportunity is presented to explore newer more space-efficient packaging concepts for IC chips.
The fastest micro-processors using MCM packaging today have about 5 nanosecond (NS) cycle time. It is becoming increasingly evident that 2-D MCM packaging-techniques will not achieve significant improvements beyond 5 NS, making newer concepts extremely attractive.
Recognizing the limitations of two-dimensional MCM packaging technology, a number of companies including Irvine Sensors, Texas Instruments (TI) and Thomson have developed 3-D multilayer IC packaging techniques which involve stacking IC chips in the third dimension as shown in FIG. 2. In general, the basic idea here is to control the size of the IC chips with precision dicing, stack them vertically, bond them together, polish one or more sides and deposit wires on the polished sides to interconnect the chips. While these prior art 3-D packaging approaches have been shown to work, they have many shortcomings and drawbacks, including: limitations on the number of IC chips which can be stacked vertically; very high manufacturing costs; and complex interconnection schemes.
Texas Instruments (TI) and Thompson are using a stacked tape-automated bonding (TAB) approach which has significant limitations in that the number of vertically-stacked chip layers is 20 or less.
Irvine Sensors Corporation (ISC) is pursing an approach that is more promising, although it too suffers from the following limitations: the number of layers of IC chips that can be stacked is limited to less than 100 because of alignment difficulties inherent in the manufacturing method; the number of layers which can be interconnected is limited unless each chip is individually personalized, a step that increases cost dramatically; the edge wiring density is low due to inaccurate alignment between the vertically disposed chips; the low yield and high cost because tested chips must have sizes with narrow tolerances to achieve certain alignment accuracy; the manufacturing process is too costly as the number of layers approaches 100; thermal and mechanical consideration add to manufacturing difficulties (i.e. heat must be carried to the edge of the stack for removal of IC chip layers and on an interchip bonding layer must be provided between to avoid delamination due to thermal mismatch); and the lack of flexibility in stack size.
In addition to the above-described activity in the 3-D packaging art, a number of 3-D IC packaging techniques have been proposed in the following U.S. Letters Patent. In U.S. Pat. No. 4,525,921, entitled xe2x80x9cHigh-Density Electronic Processing Package-Structure and Fabricationxe2x80x9d, a high density electronic package module has been proposed, comprising a stack of semiconductor chips having integrated circuitry on each chip. To permit the emplacement of thin film circuitry on the access ends, the access plane is etched to cut back the semiconductor material and then covered with passivation material. Thereafter, the passive material is lapped to uncover the ends of electrical leads on the chips. The leads are then connected to end plane wiring which is formed on two edges of stacked semiconductor chips. Chips are stacked in a supporting frame and bonded together using a thermally cured epoxy which remains over the whole surface area disposed between pairs of chips. In the arrangement disclosed in U.S. Pat. No. 4,525,921, the conductors which extend from the stacked chips extend beyond the ends of the chips by etching back the semiconductor material.
In U.S. Pat. No. 4,764,846 entitled xe2x80x9cHigh Density Electronic Package Comprising Stacked Sub-Modulesxe2x80x9d, a high density electronic package has been proposed, wherein a stack of layer-like sub-modules have their edges secured to a stack-carrying substrate. The latter is in a plane perpendicular to the planes in which the sub-modules extend. Each sub-module has a cavity inside which one or more chips are located. Each cavity-providing sub-module may be formed either by securing a rectangular frame to a chip-carrying substrate or by etching a cavity in a single piece of material. In the latter case, chips are mounted on the flat surface of one sub-module, and located inside the cavity of the next sub-module. In this reference, an electronic module is formed by first constructing a plurality of individual chip carriers, each of which has a chip mounted in a cavity in the carrier. Then, the chip carriers are secured together in a laminated stack, and the stack as a unit, is secured to a wiring board or stack carrying substrate, wherein wiring which lies in a plane parallel to the plane of the chip. Thus, in the reference, chips are placed on substrates which are then placed in chip carriers and the chip carriers are stacked to form a module.
In U.S. Pat. No. 4,706,166 entitled xe2x80x9cHigh-Density Electronic Modules-Process and Productxe2x80x9d, a high density electronic module has also been proposed, wherein integrated circuit chips are stacked. The stacked chips are glued together with their leads along one edge so that all the leads of the stack are exposed on an access plane. Bonding bumps are formed at appropriate points on the access plane. A supporting substrate formed of light transparent material such as silicon, is provided with suitable circuitry and bonding bumps on its face. A layer of insulation is applied to either the access plane or the substrate face, preferably the latter. The bonding bumps on the insulation-carrying surface are formed after the insulation has been applied. The substrate face is placed on the access plane of the stack, their bonding bumps being aligned and then bonded together under heat and pressure. A layer of thermally conductive (but electrically non-conductive) adhesive material is inserted between the substrate and stack. The substrate and stack combination is then placed and wire bonded in a protective container having leads extending therethrough for external connection.
In general, the 3-D Electronics packaging schemes disclosed in the above referenced US Letters Patents suffer from the shortcomings and drawbacks described hereinabove.
In view of the state of knowledge and skill in the art, it is clear that three-dimensional stacking of rigid IC chips as a packaging concept is known in the integrated circuit packaging art. However, this packaging technique suffers from numerous shortcomings and drawbacks which prevent it from being widely used in commercial practice. Thus, there is a great need for improved ways and means of packaging electronic circuitry in order to overcome the shortcomings and drawbacks of prior art technology.
Accordingly, a primary object of the present invention is to provide an improved method and apparatus for packaging multi-layered integrated circuits in a way which avoids the shortcomings and drawbacks of prior art technologies.
Another object of the present invention is to provide an improved three dimensional integrated circuit (IC) chip packaging method that enables stacking together thousands of integrated circuit layers realized on very thin and flexible layers, referred to as xe2x80x9cfillo-leafxe2x80x9d circuit layers, and binding together the same along one end thereof to form a massive fillo-leaf circuit layer (MFT) module.
Another object of the present invention is to provide an improved three-dimensional multilayer IC chip package for integrated circuits which incorporates flexible or rigid semiconductor elements called fillo-leaf circuit layers, on which integrated circuits in the form logic circuits or memory arrays are disposed and between which a heat carrying medium can flow for improved thermal management.
Another object of the present invention is to provide an improved three dimensional multilayer IC chip packaging technology, wherein a novel massive IC chip selection architecture (MSA) is employed in order that tens of thousand of IC circuit layers can be addressed with a minimum number of wiring connections.
Another object of the present invention is to provide an improved multilayer IC chip packaging technology, wherein the massive IC chip selection architecture enables one to vertically stack, for example, 16,384 (or 214) circuit layers, and providing each such fillo-leaf circuit layer with a unique address using only 14 wiring lines.
Another object of the present invention is to provide such an improved multilayer IC chip packaging design that enables advanced DRAM circuit layers (256M-bit to 1G-bit) to be fully interconnected so as to form 3-D MFT modules that have TerraBit(TB) storage capabilities and occupy 2-4 cm3 of space or less.
Another object of the present invention is to provide such an improved form of multilayer IC chip packaging technology, wherein it is possible to achieve electronic information storage and retrieval capacities in the TerraBit (TB) to PetaBit (PB) range.
Another object of the present invention is to provide such an improved form of multilayer IC chip packaging technology, which enables the performance levels of massively parallel processing systems to be extended into the Tera-OPS to Peta-OPS range.
Another object of the present invention is to provide an improved manufacturing infrastructure which enables unprecedented levels of multilayer IC chip packaging density capable of satisfying the needs of the high performance computers (HPC) having Peta-OPS and Peta-Bit capacities.
Another object of the present invention is to provide an improved manufacturing infrastructure that enables high-throughput production of MFT modules, and ultra-high performance MFT-based systems.
Another object of the present invention is to provide a novel method of stacking together thousands of 5 xcexcm thick silicon fillo-leaf circuit layers and interconnecting them into higher performance systems (MFT stacks) in an economical and reliable manner.
Another object of the present invention is to provide a novel method of vertically layering thousands (i.e. 1,000 to 10,000) thinned IC wafers in order to achieve unprecedented levels of memory and logic density.
Another object of the present invention is to provide an improved method and apparatus for producing, handling, stacking, and interconnecting ultra-thin IC circuit layers of 5 xcexcm thickness or less in an automated manner.
Another object of the present invention is to provide a novel form of Massive Chip Selection Architecture (MSA) which avoids the costly personalization of each IC chip layer, by carrying out a single metallization step at the bonded edge of the circuit layers in order to allow N lines to select 2N vertically stacked circuit layers (e.g. for N=14), 16,384 layers can be interconnected and uniquely addressed using only 14 wires.
Another object of the present invention is to provide a novel method of achieving high edge-wiring density within a 3-D multilayered IC chip package using a novel alignment technique that ensures alignment accuracy better than 1 xcexcm.
Another object of the present invention is to provide a novel multilayer IC chip packaging system design that enables an improved measure of thermal management.
Another object of the present invention is to provide apparatus for the manufacturing MFT devices of the present invention comprising 400 or more layers of CMOS chips, wherein each chip is provided with the MSA function plus some logic function.
Another object of the present invention is to provide a novel way of increasing the volumetric circuit densities of multilayered IC chip packages to unprecedented levels, while minimizing propagation delays and improving performance well beyond the level presently possible using prior art technologies.
Another object of the present invention is to provide a novel multilayer IC chip packaging technique which enables tens of thousands of stacked, flexible circuit layers to be addressed using a minimum number of interconnection lines, and shortest propagation delays.
Another object of the present invention is to provide a novel method of fabricating a three-dimensional multilayer IC chip package involving the steps of formatting radiation-transparent edge portions within each IC chip on each wafer so that, upon stacking thinned wafers, ultra-violet (or other radiation) curable material is fixed in order to bond fillo-leafs circuit layers together only at passivation on each IC chip, and also encoding each fillo-leaf circuit layer to provide each layer with its own unique address.
Another object of the present invention is to provide a novel multilayer IC chip packaging technique which enables unprecedented levels of information storage retrieval capacity within diverse types of systems and devices.
The objects of the present invention can achieved by providing a novel three-dimensional package for IC chips provided on multiple layers of wafer material. The novel package design comprises a plurality of subassemblies or fillo-leaf circuit layers made of materials such as silicon, germanium, gallium arsenide, sapphire or lithium niobate. The fillo-leaf circuit layers are bonded together at a radiation-transparent edge portion by an ultra-violet or other radiative light curable material, and extend in a cantilevered fashion from the bonded edge. The fillo-leaf circuit layers carry integrated circuits (ICs) like CMOS circuits, silicon-on-sapphire, superconducting Josephson circuits, fiber optic circuits and the like. Whatever technology is used, each IC has data transmission lines which extend from the circuits used to the bonded edges of the fillo-leaf circuit layers. Some of these are the usual data, address and power lines. Pairs of lines called encoder lines, are connected to a comparator or similar means and extend to the bonded edges of the IC chips.
Once the stack of fillo-leaf circuit layers is formed, by dicing and/or slicing operations carried out on a stack of bonded wafers, the bonding edges are polished, exposing inter alia, the tips of the encoder lines and providing a planar surface. Thin-film conductors are then formed on the planar surface. Among such thin-film conductors are shorting straps or interconnections which either short-circuit pairs of encoder lines or leave them open. In this way, current either flows in a pair of encoder lines or it does not, providing a unique digitally coded address for each fillo-leaf circuit layer in a stack of such structures. Each fillo-leaf circuit layer in a stack or module of one-thousand fillo-leaf circuit layers may be encoded permitting fillo-leaf circuit layers to be by-passed or selected pursuant to a stored program depending on their operating status determined though testing. Other lines formed on the radiation-transparent edge portions of the fillo-leaf circuit layers carry out known functions and may be connected via interconnections to a flexible connector to the outside which provides data and/or power signals. The fillo-leaf circuit layers in the resulting package may be flexible or rigid and cooled by a fluid coolant such air or other heat exchanging medium. Each fillo-leaf circuit element may carry logic circuits or memory arrays or combinations of both, and stacks or modules of ganged fillo-leaf circuit layers may be diced from thinned wafers to provide massively parallel data processors.
The three-dimensional IC chip packaging module of the present invention and its subassemblies are fabricated starting at the wafer level where a plurality of IC chip layers are formed on each wafer with the encoder and transmission lines of each IC chip layer extending to one edge thereof. Each IC chip is on a raw wafer provided with simple logic circuits, and the I/O ports from these circuits are brought out to one edge of the IC chip and radiation-transparent channels (or regions) are created in those wafers running parallel to the I/O circuit edges. The radiation-transparent edge channels (or regions) on each IC chip will enable UV or other radiation to be transmitted through each IC chip layer (i.e. thinned wafer) and onto a radiation-curable adhesive layer applied to thinned wafers during the stacking and bonding steps of the fabrication process. Glass channels can also be formed to allow the wafer substrate to be thinned by grinding/etching and polishing to 10-20 xcexcm. Alignment marks are applied to the wafers for use when stacking multiple wafers. Such fractures allow full automaton of IC layer alignment through the use of optical comparators or like devices.
The wafers are subjected to a thinning step so that the thinned wafer, when diced, provides flexible fillo-leaf circuit layers. The thinned wafer then has a heat dissipating element formed on its underside. The wafer is then masked and a window, transparent to ultra-violet light or other radiation, is formed at an edge of each fillo-leaf circuit layer by oxidation or, in the instance of a sapphire substrate, by masking with the heat dissipating element. A wafer is then aligned to a common fixed reference using alignment marks on the wafer. An ultra-violet light curable material is spread on the wafer and another wafer aligned over it. Ultra-violet light is beamed at the wafer such that it passes through the U.V. transparent windows curing the light curable material in registry with the windows. The uncured material is later removed.
After the desired number of thinned wafers have been stacked, the wafer stack is diced into a plurality of fillo-leaf circuit layer modules each consisting of a plurality of fillo-leaf circuit layers. Each module is then polished on the bonded edge portion so that all interconnection lines terminate at the outer edge of the same edge portions and interconnects formed which include shorting straps for selected pairs of encoder lines. Pairs of strapped interconnection lines identify each fillo-leaf circuit layer with its own code to permit selection of circuits or arrays on the semiconductor fillo-leaf circuit layer. Other interconnections carry address information, data and power to these circuits. Once these interconnections have been formed, one or more interconnect levels incorporating vias may be fabricated within the last level for connecting to data and power sources. The modules are fluid cooled and may be ganged together to permit massively parallel data processing.
The innovative architectures embodied in multilayered IC chip packaging system of the present invention should enable significant improvements in the performance of (i) massively parallel processing systems beyond the Tera-OPS to Peta-OPS range, and (ii) ultra mass storage systems beyond the Tera-Bit to Peta-Bit range.